1. Technical Field
This disclosure generally relates to computer hardware testing and utilization, and more specifically relates to a system and method for synchronization of multiple hardware agents in a computer system where the agents do not share a hardware synchronization system.
2. Background Art
Many computer systems include multiple components or agents that communicate on a common bus. The agents include processors and other components connected to the bus such as graphics processing units (GPUs). In some cases the agents access a common memory system. Computer systems with multiple processors typically have hardware methods for synchronization of the processors such as using barrier registers or atomic operations. However, these hardware synchronization methods do not allow synchronization of the non-processor agents in the computer system.
There are times where synchronization of the agents beyond the processors would be advantageous. For example, to stress test the memory model of a computer system it is important to test data sharing between the agents in the common memory system. When testing a computer system, test cases attempt to stress various timing scenarios and operations, including the coherency of memory. Coherency in the memory involves insuring that changes to data in a memory cache are accurately reflected to main memory to keep the data consistent. Synchronization of the agents before they access the shared memory insures data access collisions to stress test the common memory system.